The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device including a plurality of kinds of field effect transistors having gate insulating films of different thicknesses.
One of the techniques supporting the high integration of a semiconductor memory is known as element isolation. The element isolation of a semiconductor integrated circuit-device using the 0.25-microns technique, such as a random access memory (hereinafter abbreviated to the DRAM) of 64 Mbits, has been developed from the LOCOS (Local Oxidation of silicon) element isolation of the prior art to the so-called groove type element isolation, in which element forming regions are insulated and isolated by forming grooves in the element isolating regions of a silicon substrate and by forming a buried insulating film in the grooves. This groove type element isolation enables an element isolation length of 0.3 microns or less, which has been impossible to achieve by the LOCOS element isolation, thereby to improve the degree of memory isolation greatly.
Meanwhile, in addition to the market needs for a lower voltage and small power consumption, the rapid spread of portable devices, such as the PDAs (Personal Digital Assistants) and electronic still cameras, has intensified the demand for the simultaneous on-chip location of the elements which have been formed in different chips in the prior art. For example, microcomputers have been manufactured having a built-in flash memory or microcomputers having a built-in DRAM of an intermediate capacity have been manufactured.
On these semiconductor integrated circuit devices having devices of different functions, there are mounted a plurality of kinds of field effect transistors having different operating voltages. For the operations to write/erase information in/from the flash memory, for example, a voltage as high as 15 to 20 [V] is required, so that in part of the peripheral circuits, field effect transistors having a gate insulating film with a thickness of 15 to 25 [nm] capable of withstanding such a voltage application are used. In the logic circuit section of the microcomputer operating at an ordinary voltage of 3.3 [V], there are used field effect transistors having a gate insulating film with a thickness of 7 to 10 [nm]. In order to realize highs-peed operation at a supply voltage as low as about 1.8 [V] in a microcomputer with a built-in flash memory according to the 0.25 micron technique of recent years, there are used in the logic circuit section, field effect transistors which have a gate insulating film with a thickness of 4 to 5 [nm]. In order that the input/output units may operate also at 3.3 [V], it is necessary to form gate insulating films of three types: a gate insulating film having a thickness of 4 to 5 [nm] (for 1.8 [V]); a gate insulating film having a thickness of 7 to 10 [nm] for 3.3 [V]); and a gate insulating film having a thickness of 15 to 25 [nm] (for a flash memory). In short, it is necessary to form gate insulating films having three different thicknesses.
We have discovered the following problem by investigating the technique used when two kinds of gate insulating films having different thicknesses are separately formed over two elements forming regions of the silicon substrate, insulated and isolated by the aforementioned groove type element isolation. This problem will be described with reference to FIGS. 40(A) to 46. Of FIGS. 40(A) to 46, FIGS. 40(A) to 44 are sections for explaining the problem, FIGS. 40(A) to 42 are sections (corresponding to a later-described FIG. 2) of a field effect transistor, taken in the gate length direction, and FIGS. 43 and 44 are sections (corresponding to a later description referring to FIG. 3) of a field effect transistor, taken in the gate width direction. FIG. 45 is a diagram for comparing the breakdown voltage distribution (a) of a capacitor with the groove type element isolation and the breakdown voltage distribution (b) of a capacitor with the LOCOS element isolation. FIG. 46 is a diagram for comparing the sub-thresh characteristics (a) of a field effect transistor with the groove type element isolation and sub-thresh characteristics (b) of a field effect transistor with the LOCOS element isolation. In FIG. 45, the abscissa indicates a capacitor gate applied voltage, and the ordinate indicates the cumulative number of defects. In FIG. 46, the abscissa indicates the gate voltage, and the ordinate indicates the drain current.
First, as shown in FIG. 40(A), the groove type element isolation is achieved by forming grooves 152 for defining a first element forming region and a second element forming region in element isolating regions of a main surface of a silicon substrate 151, and subsequently by forming a buried insulating film 153 of a silicon oxide film in the grooves 152. After this, an impurity introducing buffer insulating film 154 is formed over the first element forming region and the second element forming region. After this, channel implantation layers 155A and 155B for controlling the threshold voltages of the field effect transistors are individually formed in the individual surface layers of the first element forming region and the second element forming region.
Next, the buffer insulating film 154 is removed, and thermal oxidation is then executed to form a gate insulating film 156 made of a thermally oxidized (SiO2) film having a thickness of about 20 [nm], over the first element forming region and the second element forming region, as shown in FIG. 40(B).
Next, a mask 157 is formed by using the photolithographic technique so as to cover the first element forming region, while leaving the second element forming region open.
Next, the mask 157 is used as an etching mask to remove the gate insulating film 156 from over the second element forming region by a wet-etching method using an aqueous solution of hydrofluoric acid, as shown in FIG. 41(C).
Next, the mask 157 is removed, and thermal oxidation is executed to form a gate insulating film 158 of a thermally oxidized (SiO2) film having a thickness of about 5 [nm], over the second element forming region, as shown in FIG. 41(D). At this step, the gate insulating film 156 and the gate insulating film 158 of different thicknesses can be separately formed over the first element forming region and the second element forming region which are insulated and isolated by the groove type element isolation.
Next, gate electrodes 159 of a polycrystalline silicon film doped with an impurity are individually formed over the first element forming region and the second element forming region. After this, a pair of semiconductor regions 160 for the source region and the drain region are formed in the surface layer of the first element forming region. After this, a pair of semiconductor regions for the source region and the drain region are formed in the surface layer of the second element forming region. Thus, there are formed a field effect transistor Q12 and a field effect transistor Q13 having gate insulating films of different thicknesses, as shown in FIG. 42. Here, the individual gate electrodes of the field effect transistors Q12 and Q13 are so formed that their gate electrodes in the gate width direction are led out over the buried insulating film 153, as shown in FIGS. 43 and 44.
In the separate formation of the gate insulating films by the technique of the prior art, when the gate insulating film 156 is removed from the second element forming region by a wet-etching method, the buried insulating film 153 buried in the grooves 152 is simultaneously etched off, as shown in FIG. 41(C). As a result, a step exposing the side faces of the second element forming region is formed in the end portions of the element isolating regions between the second element forming region and the element isolating region. According to the experiments made by the inventors, a step 25 [nm] is formed in the case of the gate insulating film, which is formed so as to have a thickness of 4.5 [nm] over the second element forming region. There are two major problems caused by this step.
The first problem is that the gate insulating film 158 is thinned by the mechanical stress concentration on the stepped portion, as indicated by arrow 162 in FIG. 44, at the end portions of the element isolating regions between the second element forming region and the element isolating region, so that the reliability of the gate insulating film 158 is deteriorated. In the groove element isolation, as shown in FIG. 45 by characteristic (a), the breakdown voltage is lowered by 5 to 10% from that of the LOCOS element isolation, as shown in FIG. 45 by characteristic (b).
The second problem is that the characteristics of the field effect transistor Q13 are varied because the channel implantation concentration in the vicinity of the bottom of the step on the side faces of the second element forming region drops to a lower level than that of the channel implantation layer 155b of the flat portion, as indicated by arrow 163 in FIG. 44. In the groove type element isolation, as shown in FIG. 46 by characteristic (a), the phenomenon called a kink in which the voltage current characteristics change in the course occurs, causing problems, i.e., a drop in the threshold voltage of the field effect transistor Q13, and a variation thereof.
An object of the invention is to provide a technique which is capable of enhancing the reliability of a semiconductor integrated circuit device which includes a plurality of kinds of field effect transistors having gate insulating films of different thicknesses.
The above-specified and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
A representative aspect of the invention to be described herein will be summarized in the following.
There is provided a method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate, and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and which is made thinner than the gate insulating film of the first field effect transistor. The manufacturing method comprises the steps of forming a thermally oxidized film over the first element forming region and the second element forming region of the main surface of the semiconductor substrate; subsequently forming a deposited film over the main surface of the semiconductor substrate including the thermally oxidized film; subsequently removing the deposited film and the thermally oxidized film from over the second element forming region; and subsequently forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
The first element forming region and the second element forming region are individually insulated and isolated by grooves, which are formed in the element isolating regions of the main surface of the semiconductor substrate, and a buried insulating film which is buried in the grooves.
By the aforementioned means, when the deposited film and the thermally oxidized film formed over the second element forming region are removed, the etching rate of the buried insulating film can be reduced to an extent corresponding to the thickness of the deposited film because the buried insulating film is covered with the deposited film, so that it is not etched until the deposited film is removed. As a result, the step formed at the end portions of the element isolating regions between the second element forming region and the element isolating region can be reduced to avoid the deterioration and the characteristic variation of the gate breakdown voltage, which might otherwise be caused by the step, of the field effect transistors. As a result, it is possible to enhance the reliability of the semiconductor integrated circuit device.
As the ratio of the thickness of the deposited film to the thickness of the gate insulating film formed over the first element forming region increases, the thermally oxidized film formed over the second element forming region is made thinner, so that the etching rate of the buried insulating film can be reduced. The etching rate of the buried insulating film is increased in proportion to the thickness of the thermally oxidized film.